Synopsys has officially announced the launch of industry’s first Ultra Ethernet IP and UALink IP solutions,
According to certain reports, these solutions include controllers, PHYs, and verification IP, each one designed to meet the demand for standards-based, high-bandwidth, and low-latency HPC and AI accelerator interconnects.
To understand the significance of such a development, we must take into account a fact that, as hyperscale data center infrastructures evolve to support the processing of trillions of parameters in large language models, they have no option but to scale to hundreds of thousands of accelerators with highly efficient and fast connections.
Fortunately enough, Synopsys’ latest brainchild addresses that very need. We get to say so because its Ultra Ethernet and UALink IP solutions are designed to provide a holistic, low-risk medium for high-speed and low-latency communication, helping it scale-up and scale-out AI architectures.
Talk about each solution on a slightly deeper level, we begin from Synopsys Ultra Ethernet IP Solution, which allows you to scale out backend networks. More on the same would reveal how it comes decked up with PHY, MAC and PCS controller, and verification IP. Leveraging these components, the solution is able to offer a low-risk path for designers developing systems that, on their part, can support up to one million endpoints in a single network.
Next up, we must dig into its best-in-class 224G Ethernet PHY. This silicon-proven Synopsys 224G Ethernet PHY IP arrives on the scene with an ability to support the Ultra Ethernet protocol. Making the feature even more impressive is its demonstration of broad interoperability, as shown at multiple tradeshows including ECOC, OFC, and DesignCon.
Then, we have the solution’s patented error correction implementation facility. In essence, Synopsys Ultra Ethernet MAC and PCS controller IP provides up to 1.6 Tbps of bandwidth with ultra-low latency, thus enabling the real-time processing needed for AI workloads.
Another detail worth a mention here is rooted in the solution’s promise to facilitate seamless integration. Basically, MAC and PCS IP supports an interface to the higher layers of the Ultra Ethernet stack providing a full silicon implementation for switches, AI accelerators and smart NICs.
Rounding up highlights for Synopsys Ultra Ethernet IP solution would be its big to accelerate verification and validation capacity, which enables protocol adherence to rapidly evolving standards, and therefore, support faster and more efficient validation of AI and HPC systems.
“Juniper has already introduced the industry’s first 800GbE capability with its PTX10002-36QDD Packet Transport Router, which utilizes our proprietary Express 5 ASIC with Synopsys Ethernet IP,” said Debashis Basu, senior vice president of Juniper Engineering. “We will continue to partner with Synopsys and leverage the latest technologies from the Ultra Ethernet Consortium (UEC) to transition into the 1.6TbE era. This indicates our ongoing innovation in high-speed networking to achieve our goal to significantly improve scale, reliability, and performance in data center networks.”
Turning our attention towards Synopsys UALink IP, it can tread up a long distance to help you scale up computing fabrics. This it does with the help of PHY, controller, and verification IP, using the same to speed time-to-market for designers developing systems that can support up to 1,024 AI accelerators.
Next up, it ought to be acknowledged how the solution in question can offer you efficient high-speed data transfers. Engineered for data-intensive AI workloads, the low-power and high-bandwidth Synopsys UALink PHY IP is able to effectively provide 200 Gbps per lane.
Markedly enough, Synopsys UALink IP is also latency-optimized with memory sharing capabilities, something which allows it to mitigate critical bottlenecks of AI hardware infrastructure via shared memory access from accelerator to accelerator.
“For more than 25 years, Synopsys has been at the forefront of providing best-in-class IP solutions that enable designers to accelerate the integration of standards-based functionality,” said Neeraj Paliwal, senior vice president of IP product management at Synopsys. “With the industry’s first Ultra Ethernet and UALink IP, companies can get a head start on developing a new generation of high-performance chips and systems with broad interoperability to scale future AI and HPC infrastructure.”
