Intel Corp (INTC.O) research teams announced work on Saturday that they believe will enable them to continue to speed up and downsize computing devices over the next 10 years, with multiple technologies focused on stacking sections of chips on top of each other.
The work was presented in papers at an international conference in San Francisco by Intel’s Research Components Group. The Silicon Valley firm is attempting to reclaim a lead in the production of the smallest and fastest processors that it has lost to rivals such as Taiwan Semiconductor Manufacturing Co (2330. TW) and Samsung Electronics Co Ltd in recent years (005930. KS).
While Intel CEO Pat Gelsinger has laid out commercial ambitions to reclaim that position by 2025, the research study released on Saturday provides insight into how Intel aims to compete beyond that date.
Intel is cramming more computing power into chips by stacking “tiles” or “chiplets” in three dimensions rather than constructing the entire chip in two dimensions. Intel demonstrated work on Saturday that might allow for ten times as many connections between stacked tiles, allowing for the stacking of increasingly complicated tiles on top of each other.
A research study describing a way to stack transistors – small switches that form the most fundamental building blocks of chips by encoding the 1s and 0s of digital logic – on top of one another was possibly the most significant improvement shown Saturday.
Intel estimates that the method will improve the number of transistors it can pack into a particular area on a chip by 30% to 50%. The main reason chips have continually increased quicker over the last 50 years is through increasing the number of transistors.
